Dual-edge clocking is used in a variety of applications to take advantage of both the rising and falling edges of a clock signal. Dual-edge clocking can provide improved performance at lower power by enabling reduced clock speeds for an integrated circuit. However, many integrated circuits implement multiple clock signals, where data may pass from one clock domain to another. That is, data sent from one register that is configured to receive a first clock signal associated with a first clock domain may be received by a register that is configured to receive a second clock signal associated with a second clock domain, and therefore must cross the clock domain.
Registers implemented in an integrated circuit may be a part of a scan chain to enable testing of the integrated circuit. Because scan chains that cross clock-domains may have an excessive amount of clock skew at clock-domain cross-over points, testing of the integrated circuit may lead to particular problems when performing testing using a scan chain in an integrated circuit having dual-edge clocking associated with registers in different clock domains. The testing of a scan chain using dual-edge clocking may not only be incomplete, but may also lead to errors in the testing based upon indeterminate test values at certain points of the scan chain. More particularly, when implementing design for test and design for debug with dual-edge clocking, errors during testing may occur when a register of a dual-edge clocking circuit is not tested or an incorrect signal is applied during testing.
Accordingly, circuits and methods that implement a scan chain in an integrated circuit having a clock domain crossing and overcome the deficiencies of conventional circuits are beneficial.